The following topics will be covered in the workshop. Fundamentals of filter design methodologies such as Active RC filters, OTA-C filters, Current-mode filters, Switched capacitor filters, Effect of non-ideal passive and active components such as tolerances of components, Finite gain, bandwidth of active devices, noise of passive and active devices, offset of active devices, parasitics due to interconnections as well as inherent parasitics, Recent trends in filter design for various mobile devices using GSM, CDMA.
Registration starts from 18 May, Registration closes by 13 June, Click here for Brochure. Click here for Registration.
100+ VLSI Projects for Engineering Students
Click here for Agenda. Designers are required to design their circuits with the help of EDA tools. Increased complexity and performance of systems on chip e. Faster time to market requires seamless and predictable PD flows with high sign off QoR to ensure high yield in deep submicron process nodes 28nm and beyond.
Apply advanced technologies in the fields of VLSI design along with the fundamental concepts. Facilitatethe students using industry standard EDA tools and adopt sign-off design methodology for realizing complex VLSI systems for a given specification. Understand the complexities and design methodologies of current and advanced IC design technologies.
Identify, formulate, and solve VLSI design problems using advanced level manufacturing techniques.
Able to plan, conduct an organized and systematic study on significant research topic within the field of VLSI and its allied field. The course focuses on performance metrics of processor and system architectures. The course helps you understand fundamental metrics used for quantitative evaluation of a design. It focuses on basics of MOS transistors and CMOS technology, combinational and sequential schemes, principles of design of digital units, modules of memory and other arithmetic circuits.
IC Design using VLSI
It also helps you develop skills to design different memory elements and building blocks in digital circuits using Verilog language. Course Objectives: Understand fundamental metrics used for quantitative evaluation of a design Learn the basics of MOS transistors and CMOS technology, combinational and sequential schemes, principles of design of digital units, modules of memory and other arithmetic circuits Apply the concepts of high level digital design using Verilog Hardware Description Language Understand the principles of design, analysis and simulation of digital circuits Design different memory elements and building blocks in Digital circuits Understand the concepts of timing issues in digital design.
Course Objectives: Learn variousverification techniques. Learn the principles of verification, and use of SystemVerilog for verification Use System Verilog for efficient verification. Learning Outcomes: Understand the principles of verification and different test bench architectures used for verification ApplyOOPS concepts in System Verilog Build basic verification environment using System Verilog Generate random stimulus and track functional coverage using SV Perform constrain driven verification, assertion based verification and coverage driven verification using System Verilog Apply the concept of Layered test bench architecture and its components.
EE : Advances in VLSI Circuit Design
This in turn, will help you to automate different processes in ASIC flow. Course Objectives: Learn architectural elements, performance metrics and system architecture of computer systems Learn the concepts of verification components, test bench structure and Transaction-Level Modeling TLM Perform system-level verification with Universal Verification Methodology UVM. Learning Outcomes: Learn the application of various protocol and interfaces Build and manage stimulus sequencers, drivers and monitors Build reusable verification components and environment using UVM Create reusable stimulus sequences, including for multi-layer protocols Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects.